1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, relates to a dynamic random access memory (DRAM) and a method for fabricating the same.
2. Description of the Related Art
In order to reduce unit area of memory cells of a dynamic random access memory (DRAM), a vertical transistor structure has been widely used. In the vertical transistor structure, active regions of transistors are formed in a single crystal semiconductor substrate. Storage capacitors are formed on the top of the active regions. Bit lines and word lines are buried in the semiconductor substrate. Each of the bit lines and each of the word lines are electrically connected to the active regions of the transistors. The variation of electron charges which are stored in the storage capacitors is controlled by the bit lines and the word lines.
At present, many methods for forming a buried bit line have been disclosed. For example, U.S. Pat. No. 7,355,230 discloses a method for forming a buried line. In this method, a channel region of a transistor is formed in a trench surrounded by an insulation liner layer. The trench has an opening formed only on one sidewall and a contact is filled in the opening for electrically connecting the bit line to the channel region of the transistor. However, the process of forming an opening only on one sidewall of the trench is very complicated and results in a poor process window. Thus, to develop a DRAM having the vertical transistor which can address the above issues is needed.